1. Field of the Invention
The invention relates generally to a universal logic structure and more particularly to a dual input universal logic structure for implementing VLSI logic and memory.
2. Description of the Relevant Art
The design of digital circuitry to implement a logical function has primarily involved interconnecting basic logic elements such as AND, OR, NAND, NOR, and inverter gates. After a designer has determined the logical equation to be implemented by circuitry, the basic logic gates may be interconnected in a straight-forward approach to implement the logical function. The number of gates required is usually dependent upon the number of terms and the form of the logical equation to be implemented. It is usually desirable to minimize the number of logical elements used, and there are many techniques which allow a designer to reduce the logical equation in order that the number of gates required may be minimized.
The term "logic design" refers to the process of specifying an interconnection of logic elements in digital computer hardware so that a desired function is performed. Examples of this process might be the design of a circuit that accepts data representing numbers in a gray code and converts this data into a binary-coded decimal representation, or the design of a multiplexer circuit that provides input data from one of two input lines to an output line depending upon the value of a control line. Both formal and ad hoc techniques are used to achieve the desired design.
The basic logic gates are the smallest building blocks that can be represented by operators in an appropriate system of symbolic logic. All digital logic networks in current use operate on signals that are restricted to two possible values only, and are thus called binary values. Table 1(a)-(e) lists each possible combination of binary signals at the inputs of the basic logic gates and the corresponding combination of desired output signals.
TABLE 1(a)-1(e) ______________________________________ Inputs Output ______________________________________ (a) Inverter 0 1 1 0 (b) AND gate 0 0 0 0 1 0 1 0 0 1 1 1 (c) OR gate 0 0 0 0 1 1 1 0 1 1 1 1 (d) NAND gate 0 0 1 0 1 1 1 0 1 1 1 0 (e) NOR gate 0 0 1 0 1 0 1 0 0 1 1 0 ______________________________________
Each of the basic logic gates is internally composed of electronic components interconnected to perform the associated logical function, typically including a number of CMOS transistors. FIGS. 1(a)-(e) show typical internal circuitry within each of the corresponding basic logic gates. As shown in FIG. 1(a), a NOT gate 10 comprises two CMOS transistors 11 and 12. A two-input NAND gate 13 comprises four CMOS transistors 14-17 as shown in FIG. 1(b). Similarly, a two-input NOR gate 20 shown in FIG. 1(c) comprises four CMOS transistors 21-24. As shown in FIG. 1(d), a two-input AND gate 25 comprises six CMOS transistors 26-31. Finally, as shown in FIG. 1(e), a two-input OR gate 32 comprises six CMOS transistors 33-38. Although there are circuit configurations other than those shown in FIGS. 1(a)-1(e) which may be designed to implement the logical functions represented by Tables 1(a)-1(e), the circuit configurations as shown represent the simplest forms which require the fewest number of transistors to implement the associated logical functions.
FIG. 2(a) shows a logic diagram of a multiplexer 40 designed using the basic logic gates. Multiplexer 40 includes inverter gates 41 and 42, AND gates 43 and 44, and NOR gate 45. If conventional logic were used to construct multiplexer 40, the resulting overall internal circuit configuration would be as shown in FIG. 2(b). The logic equation implemented by multiplexer 40 is: EQU OUT=A.sub.1 .multidot.B.sub.1 +A.sub.2 .multidot.B.sub.2 eq. ( 1)
As shown in FIG. 2(b), when multiplexer 40 is designed using conventional logic, the resulting overall internal circuit consists of a total of twelve CMOS transistors 46-57.
FIG. 3(a) is a logic circuit of an exclusive NOR gate 60 implemented using conventional logic. Exclusive NOR gate 60 consists of two inverters 61 and 62, and two transmission gate switches 63 and 64. Since a transmission gate switch comprises two CMOS transistors 65 and 66 as shown in FIG. 3(b), exclusive NOR gate 60 internally consists of eight CMOS transistors 67-74 as shown in FIG. 3(c).
FIG. 4 shows a logical circuit which implements a decoder function. A two-input, four-output decoder 75 shown comprises two inverter gates 76 and 77 and four NAND gates 78-81. Thus, when logic gates having internal circuitry as shown in FIGS. 1(a) and 1(b) are used to implement the decoder function, the resulting circuit comprises a total of twenty CMOS transistors.
In VLSI (very large scale integration) circuitry, a large number (i.e., over ten thousand) of the basic logical gates may be fabricated on a single integrated circuit chip. The number of basic logic gates used dictate the number of actual FETs which are fabricated on the integrated circuit chip, and consequently determine the size requirements of the chip. It is desirable to decrease the size requirements of VLSI chips and to minimize the number of CMOS transistors used to implement a given logical equation. In addition, it is further desirable to increase the speed at which VLSI circuitry may operate.